Integrated circuit electronic memory arrays having a plurality of one device FET memory cells are notoriously well known in the art. Such an array of memory cells was first proposed in Dennard U.S. Pat. No. 3,387,286 entitled: "Field-Effect Transistor Memory". Subsequently, various improvements were made primarily in the fabrication processes, layout techniques, and support circuits.
A well known semiconductor integrated circuit process is the self-aligned silicon gate process. In this FET process, silicon gate regions (usually polysilicon) are formed prior to the formation of doped source and drain regions. Source and drain regions are known to be formed by both diffusion and ion implantation processes and are self-aligned to the gate region by virtue of the fact that the gate is utilized as the mask. This silicon gate technology, which is a polysilicon process, has been characterized by the number of layers of polysilicon conductors. Thus, there are single polysilicon (SPS), double polysilicon (DPS) and triple polysilicon (TPS) etc. processes.
In earlier versions of this technology, it was common practice for the bit line to be an elongated doped N+ region; which same region also formed the drain or source region of the one device FET memory cell. Drain and source regions are interchangeable in FETs and depend on the applied bias voltages. The bit line is electrically integral with (i.e., connected to) the doped region farthest from the capacitor. The distributed capacitance along the length of such a doped bit line is relatively high. Since the signal strength of the sense amplifier input (connected to the bit line) is a function of the transfer ratio (memory cell capacitance/bit line capacitance), a large bit line capacitance tends to reduce the useful input signal to the sense amplifier. To improve the transfer ratio, the size of the storage capacitor in the memory cell can be increased. The added space occupied by such a storage capacitor is undesirable because it reduces the number of memory cells that can be put on a semiconductor chip of a given size. Moreover, the doped bit line also has a finite resistance which together with the various capacitances including the storage capacitor adversely, affect the rised time of pulses being transfered into an out of the storage capacitor. Thus, a larger storage capacitor could result in a slower operating memory cell.
For this reason, bit lines are now commonly formed by metal conductors above the silicon surface. One example of such an arrangement is shown in Scheuerlein U.S. Pat. No 4,319,342. Another arrangement is shown in Kiyoo Itoh et al, "A High Speed 16K Bit NMOS Random Access Memory", I.E.E.E. J. Solid-State Circuits SC-11, pp.585-590, Oct. 1976. Similarly, Kiyoo Itoh et al U.S. Pat. No. 4,044,340 issued Aug. 23, 1977, shows an arrangement in which the bit lines (data lines) and word lines are located above the semiconductor surface. The Itoh patent also shows an advantageous arrangement of one device memory cells known as the folded bit line and dummy cell technique. The floded bit line technique permits the "pitch" of the bit line to be matched to the "pitch" of the sense amplifier, resulting in a saving of semiconductor space. As shown in FIG. 3 of the patent, memory cells along a column are alternately connected to true bit line D.sub.o and complementary bit line D.sub.o. Whenever one of the word lines is selected, one of the dummy word lines selects one of the two dummy bits. The selected dummy bit is always the one that is connected to the bit line opposite from the one to which the selected memory cell is connected. In this way, a differential signal is provided to the sense amplifier.
The Itoh patent arrangement has a number of disadvantages. For example, the cell illustrated in FIG. 5b has undesired capacitive coupling between metal bit line D1 and doped regions 400 and 410. Also, the arrangement appears to require a sense amplifier for each 64 bits. There is no disclosed means for increasing the bit/sense amplifier ratio without decreasing the transfer ratio.